Bias temperature instability and condition monitoring in SiC power MOSFETs

Threshold voltage shift due to bias temperature instability (BTI) is a major concern in SiC power MOSFETs. The SiC/SiO2 gate dielectric interface is typically characterized by a higher density of interface traps compared to the conventional Si/SiO2 interface. The threshold voltage shift that arises from BTI has significant implications on the reliability of SiC power MOSFETs, hence, techniques for detecting the change in electrical parameters due to gate oxide degradation are desirable. Using accelerated high temperature gate bias stress tests on SiC MOSFETs, it has been shown that the output and transfer characteristics are affected by BTI. This paper presents the impact BTI induced threshold voltage shift on the forward voltage of the SiC MOSFET body diode during third quadrant operation. Using the forward voltage of the body diode during reverse conduction of low currents, threshold voltage shift can be detected, hence, the impact of BTI can be evaluated. The implications of the body diode forward voltage shift on junction temperature measurements are also studied in the context of TSEPs. The findings in this paper are important for engineers seeking to implement condition and health monitoring techniques on SiC power devices

A novel non-intrusive technique for BTI characterization in SiC MOSFETs

Threshold voltage ( $V_{TH}$ ) shift due to Bias Temperature Instability (BTI) is a well-known problem in SiC-MOSFETs that occurs due to oxide traps in the $SiC/SiO_2$ gate interface. The reduced band offsets and increased interface/fixed oxide traps in SiC-MOSFETs makes this a more critical problem compared to silicon. Before qualification, power devices are subjected to gate bias stress tests after which $V_{TH}$ shift is monitored. However, some recovery occurs between the end of the stress and $V_{TH}$ characterisation, thereby potentially under-estimating the extent of the problem. In applications where the SiC-MOSFET is turned OFF with a negative bias at high temperature, if $V_{TH}$ shift is severe enough there may be electrothermal failure due to current crowding since parallel devices lose synchronization during turn-ON. In this paper, a novel method that uses the forward voltage of the body diode during reverse conduction of a small sensing current is introduced as a technique for monitoring $V_{TH}$ shift and recovery due to BTI. This non-invasive method exploits the increased body effect that is peculiar SiC-MOSFETs due to the higher body diode forward voltage. With the proposed method, it is possible to non-invasively assess $V_{TH}$ shift dynamically during BTI characterization tests

Crosstalk in SiC power MOSFETs for evaluation of threshold voltage shift caused by bias temperature instability

Threshold voltage drift from Bias Temperature Instability is known to be a reliability concern for SiC MOSFETs. Negative bias temperature instability (NBTI) results from positive charge trapping at the gate dielectric interface and is more problematic in SiC due to the higher interface trap density. Turning SiC MOSFETs OFF with negative voltages to avoid Miller coupling induced cross-talk can cause VTH shifts in periods with long standby duration and high temperatures. This paper proposes a novel test method for BTI characterization that relies on measuring the shoot-through current and charge during switching transients. The method exploits the Miller coupling between 2 devices in the same phase and uses the shoot-through current from parasitic turn-ON to monitor VTH. Standard techniques require the use of static measurements (typically from a parameter analyzer or a curve tracer) to determine the threshold voltage shift. These conventional methods can underestimate the VTH shift since the recovery from charge de-trapping can mask the true extent of the problem. The proposed methodology uses the actual converter environment to investigate the VTH shift and should therefore be of more interest to applications engineers as opposed to device physicists. Furthermore, it avoids the problem of VTH recovery and is therefore more accurate in VTH shift characterization

Impact of BTI induced threshold voltage shifts in shoot-through currents from crosstalk in SiC MOSFETs

In this paper a method for evaluating the implications of threshold voltage (VTH) drift from gate voltage stress in SiC MOSFETs is presented. By exploiting the Miller coupling between two devices in the same phase leg, the technique uses the shoot-through charge from parasitic turn-ON to characterize the impact of Bias Temperature Instability (BTI) induced VTH shift. Traditional methods of BTI characterization rely on the application of a stress voltage without characterizing the implication of the VTH shift on the switching characteristics of the device in a circuit. Unlike conventional methods, this method uses the actual converter environment to investigate the implications of VTH shift and should therefore be of more interest to applications engineers as opposed to device physicists. Furthermore, a common problem is the underestimation of the VTH shift since recovery from charge de-trapping can mask the true extent of the problem. The impact of temperature, the recovery time after stress removal and polarity of the stress have been studied for a set of commercially available SiC MOSFETs

Bias temperature instability and junction temperature measurement using electrical parameters in SiC power MOSFETs

Junction temperature sensing is an integral part of both on-line and off-line condition monitoring where direct access the bare die surface is not available. Given a defined power input, the junction temperature enables the estimation of the junction-to-case thermal resistance, which is a key indicator of packaging failure mechanisms like solder voiding and cracks. The use of temperature sensitive electrical parameters has widely been proposed as a means of junction temperature sensing however, there are certain challenges regarding their use in SiC MOSFETs. Bias Temperature Instability from charge trapping in the gate dielectric causes threshold voltage drift, which in SiC affects some of the key temperature sensitive electrical parameters including ON-state resistance, body diode forward voltage as well as the current commutation rate. This paper reviews the impact of bias temperature instability on the accurate junction temperature measurement using temperature sensitive electrical parameters in SiC MOSFETs

A multiphysics modeling and experimental analysis of pressure contacts in power electronics applications

This paper details a modeling and experimental assessment of the packaging process for a silicon carbide Schottky diode using pressure contacts. The work detailed in this paper is original, as it applies a combined electrothermomechanical modeling analysis to this packaging method supported by experimental validation. A key design objective for this packaging process is to identify suitable contact pad materials, heatsinks, and process variables such as clamping force to meet electrical, thermal, and reliability specifications. Molybdenum and aluminum graphite (ALG) have been identified as two suitable materials for the contact pads. Clamping forces ranging from 300 to 500 N and electric current ranging from 10 to 30 A have been investigated in terms of the resulting electrical and thermal contact resistances, temperatures, and stresses induced across the package. The performance of two heatsink designs with heat dissipation rates of 12893 and 4991 W/m2k has also been investigated. Both the modeling and initial experimental results detailed in this paper show that ALG provides better performance in terms of generating a lower average chip temperature. Both temperature and stress in the diode are predicted as a function of clamping force and load current. This will aid the packaging engineer to identify suitable process parameters to meet junction temperature requirements at different applied load currents

Robustness and reliability review of Si and SiC FET devices for more-electric-aircraft applications

Increased electrification of traditionally hydraulic and pneumatic functions on aircrafts has put power electronics at the heart of modern aviation. Aircraft electrical power systems have traditionally operated at 115 V AC and 28 V DC with a constant speed generator and transformer rectifier units converting jet engine power into electrical power. However, due to the increasing trend towards the More Electric Aircraft (MEA), 270 V DC systems are likely in the future. This calls into question, the power semiconductor device technology that enables the on-board power converters needed for electro-mechanical actuation as well as solid-state circuit breakers for system protection. Silicon IGBTs have been the work-horse of power electronics, but as switching speeds increase due to the need for high frequency operation, the bipolar nature of IGBT tail currents become a limiting factor for improved energy conversion efficiency. A number of unipolar FET technologies, including SiC trench MOSFETs, SiC planar MOSFETs, silicon super-junction MOSFETs and SiC JFETs in cascode with a low voltage Si MOSFET, have become commercialized at around 650 V. However, reliability and robustness, especially against single event burn-out and/or single event gate rupture is critical. This paper experimentally investigates the performance of the listed FET devices under Unclamped Inductive Switching and Bias Temperature Instability/gate oxide stress tests

Prospects and Challenges of 4H-SiC Thyristors in Protection of HB-MMC-VSC-HVDC Converters

Pole-to-pole DC faults on HB-MMC-VSC-HVDC schemes impose significant risk of cascade failure on IGBT/diode pairs. Other novel topologies with fault blocking capability, i.e. AAC converters, and DC circuit breakers are not yet fully matured. Therefore, silicon thyristors are used to bypass the DC faults until AC breakers activate. However, silicon thyristors are also at risk of failure due to the capacitor voltage collapse at high junction temperatures caused due to imbalanced reverse recovery current conduction. Hence, the recovery cycles are included as part of IEC standard 62 501 HVDC type-test program. Emergence of commercial Silicon Carbide (SiC) thyristors has the potential to tackle this risk. This paper investigates such opportunities and challenges by accurately modeling the performance of thyristors at fault. It was seen that SiC thyristors with acceptable surge current and reverse blocking capability can eliminate the failure mode of silicon thyristors due to minimal recovery stored charge, resulting in an equal share of reverse voltage on all thyristors

Analysis of the 1st and 3rd Quadrant Transients of Symmetrical and Asymmetrical Double-Trench SiC Power MOSFETs

In this paper, performance at 1 st and 3 rd quadrant operation of Silicon and Silicon Carbide (SiC) symmetrical and asymmetrical double-trench, superjunction and planar power MOSFETs is analysed through a wide range of experimental measurements using compact modeling. The devices are evaluated on a high voltage clamped inductive switching test rig and switched at a range of switching rates at elevated junction temperatures. It is shown, experimentally, that in the 1 st quadrant, CoolSiC (SiC asymmetrical double-trench) MOSFET and SiC symmetrical double-trench MOSFET demonstrate more stable temperature coefficients. Silicon Superjunction MOSFETs exhibits the lowest turn-off switching rates due to the large input capacitance. The evaluated SiC Planar MOSFET also performs sub-optimally at turn-on switching due to its higher input capacitance and shows more temperature sensitivity due to its lower threshold voltage. In the 3 rd quadrant, the relatively larger reverse recovery charge of Silicon Superjunction MOSFET negatively impacts the turn-OFF transients compared with the SiC MOSFETs. It is also seen that among the SiC MOSFETs, the two double-trench MOSFET structures outperform the selected SiC planar MOSFET in terms of reverse recovery